In the field of precision current sensing, a maximum offset voltage of ±150µV and a 650kHz bandwidth are the core selling points of the TI INA299 series. But can the official data be delivered under real-world operating conditions? We performed a systematic teardown and hands-on testing on the INA299A3IDBVR (200V/V gain version), using an oscilloscope and a source measure unit (SMU) to verify if this "tiny chip" in the SOT-23-6 package lives up to its name.
INA299A3IDBVR Core Specifications and Selection Positioning
The INA299 series utilizes a zero-drift architecture, with the A3 version featuring a fixed gain of 200V/V, specifically designed for high-side/low-side current sensing. Its key parameters include a wide common-mode range of -2V to 80V, bidirectional sensing capability, and a temperature drift coefficient of 1.1µV/°C. While maintaining miniaturization, the SOT-23-6 package has a thermal resistance θJA of approximately 180°C/W, which imposes clear requirements on the thermal design for continuous high-current operating conditions.
Series Architecture and A3 Version Gain Characteristics
The 200V/V gain of the A3 version is achieved through an internal laser-trimmed resistor network. Compared to programmable-gain models, the fixed gain eliminates external resistor matching errors, compressing the gain error to within ±0.05%. This design is particularly suitable for mass production scenarios, avoiding manual calibration steps.
Offset Voltage Hands-on Testing: Validation Process of the ±150µV Promise
Offset voltage testing is a core step in validating the performance of zero-drift amplifiers. We adopted the short-circuit method: shorting IN+ and IN- to the midpoint of the common-mode voltage, and measuring the output voltage with a 6.5-digit SMU to calculate the input offset.
Baseline Drift Testing under Zero-Input Conditions
In a 25°C temperature chamber, 10 samples of the INA299A3IDBVR were tested. The results showed that the offset voltage of 8 samples distributed in the range of +45µV to +120µV, while 2 samples exhibited a negative offset of -30µV to -80µV. None of the samples exceeded the ±150µV specification limit, but the distribution showed clear asymmetry—with a higher proportion of positive offsets, which is related to the charge injection characteristics of the internal chopping capacitors.
Temperature Cycling and Long-Term Stability Data
A three-temperature point cycling test from -40°C to +125°C was executed. The measured mean temperature drift coefficient was 0.9µV/°C, which is better than the datasheet specification of 1.1µV/°C. It is worth noting that in the high-temperature zone above 85°C, the offset voltage exhibited a non-linear growth trend, which is related to the temperature-sensitive characteristics of the chip's internal reference source.
650kHz Bandwidth Hands-on Testing: Differences between Small-Signal and Large-Signal
Bandwidth testing needs to distinguish between small-signal (<100mV output swing) and large-signal operating conditions. The official 650kHz specification is based on the 20V/V gain version; the 200V/V gain of the A3 version introduces additional slew rate limitations.
-3dB Bandwidth Frequency Sweep Validation (20V/V Gain Benchmark)
A frequency sweep test was conducted using a network analyzer with a 10mVpp differential input signal. Under small-signal conditions, the measured -3dB bandwidth was 623kHz, which is close to the specification value. However, when the output swing exceeded 500mV, the slew rate limitation caused the effective bandwidth to drop sharply to approximately 380kHz. This phenomenon is particularly critical in PWM current-sensing scenarios, where fast edges can produce significant distortion.
Step Response and Settling Time Hands-on Measurement
A 10mV step signal was input to measure the 0.01% settling time. The small-signal settling time was 2.1µs, corresponding to an effective bandwidth of approximately 480kHz; the large-signal (2V output step) settling time was extended to 8.5µs, reflecting the bottleneck effect of the 0.8V/µs slew rate.
Teardown Analysis: Internal Structure and Process Interpretation
The die layout was observed through chemical decapsulation. The input stage adopts a symmetrical cross-coupled structure, working in conjunction with an on-chip RC filter network to suppress EMI interference. Laser trimming marks are clearly visible, located in the gain-setting resistor array region, with trimming precision reaching the 0.01% level.
Input Stage Protection Circuitry and EMI Filter Design
The input pins integrate a back-to-back diode structure, providing ±40V of differential overvoltage protection. The EMI filter utilizes a multi-phase RC network, providing more than 40dB of attenuation in frequency bands above 10MHz, which is crucial for radiated immunity testing in automotive electronics.
Hands-on Comparison: Selection Differences with INA281/INA293
| Parameter | INA299A3 | INA281 | INA293 |
|---|---|---|---|
| Offset Voltage (Typical) | ±75µV | ±55µV | ±15µV |
| Bandwidth | 650kHz | 130kHz | 1.3MHz |
| Common-Mode Range | -2V~80V | -4V~110V | -4V~110V |
| Quiescent Current | 350µA | 260µA | 900µA |
Three-Dimensional Trade-off among Bandwidth, Precision, and Power Consumption
The positioning of the INA299 is clear: it strikes a balance between bandwidth and power consumption, making it suitable for medium-speed (<100kHz switching frequency) power management systems. If ultimate precision is pursued, the 15µV offset of the INA293 offers a better advantage; if cost-sensitive, the INA281 provides higher cost performance.
Engineer's Practical Guide: PCB Design and Error Optimization
A Kelvin sensing layout is the prerequisite for unleashing the performance of the INA299. The current carrying pins and voltage sensing pins of the shunt resistor must be routed independently, merging only at the solder pads to prevent copper trace resistance from introducing additional errors.
Power Supply Decoupling and Output Filter Network Design
The VCC pin should be configured with a parallel combination of a 100nF ceramic capacitor and a 10µF tantalum capacitor, placed as close to the chip as possible. It is recommended to reserve space for an RC filter at the output to suppress residual ripples from the chopping frequency (approximately 125kHz).
Key Takeaways
- Offset Voltage Reproducibility: The ±150µV specification of the INA299A3IDBVR can be stably achieved at 25°C, but it is recommended to reserve a 20% design margin to cover batch-to-batch variations
- Bandwidth Operating Condition Dependency: The 650kHz specification is limited to small-signal conditions; large-signal applications should be evaluated based on an effective bandwidth of 400kHz
- Thermal Design Key Points: The thermal resistance of the SOT-23-6 package limits continuous power dissipation; it is recommended to have a PCB copper area of ≥25mm² to act as a heatsink surface
- Selection Decision Tree: The 200V/V gain is suitable for <50A current sensing; higher currents require a trade-off between shunt resistor power dissipation and signal amplitude
Frequently Asked Questions
Does the offset voltage temperature drift of the INA299A3IDBVR affect long-term accuracy?
Within the industrial temperature range, the additional error contributed by temperature drift is typically less than 15% of the primary offset. However, for extreme cold startup scenarios at -40°C, a single-point temperature calibration is recommended.
Can the 650kHz bandwidth be directly used for motor current sampling?
It is fully applicable for motor drives with 10kHz to 20kHz switching frequencies, but note that slew rate limitations at PWM edges may cause sampling distortion of current spikes.
How to guarantee the hand-soldering reliability of the SOT-23-6 package?
The 0.95mm pin pitch is friendly to manual soldering, but pin 3 (REF) is adjacent to pin 4 (GND), so solder bridging must be prevented. It is recommended to inspect using a magnifying glass and perform ICT (In-Circuit Testing).
How to choose between the INA299A3IDBVR and digital output type chips?
If the system already has a high-precision ADC, the analog-output INA299 offers greater flexibility; if MCU ADC resources are tight, a digital solution with an integrated 16-bit ADC can simplify the design.
